DocumentCode
2048032
Title
Analysis of Multiple Parallel Block Coding in JPEG2000
Author
Dyer, Michael ; Nooshabadi, Saeid ; Taubman, David
Author_Institution
New South Wales Univ., Sydney
Volume
5
fYear
2007
fDate
Sept. 16 2007-Oct. 19 2007
Abstract
We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks. The system was implemented on an Altera NIOS II processor with flexible integrated peripheral.
Keywords
block codes; data compression; hardware-software codesign; image coding; parallel processing; system-on-chip; Altera NIOS II processor; JPEG2000 compression standard; SoC; flexible integrated peripheral; image coding; multiple parallel block coding; parallel coding; parallel processing; scheduling granularity; software-hardware codesign platform; system on a chip; Block codes; Communication switching; Discrete wavelet transforms; Fabrics; Hardware; Image coding; Software libraries; Software standards; Switches; Transform coding; Image coding; Parallel processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Image Processing, 2007. ICIP 2007. IEEE International Conference on
Conference_Location
San Antonio, TX
ISSN
1522-4880
Print_ISBN
978-1-4244-1437-6
Electronic_ISBN
1522-4880
Type
conf
DOI
10.1109/ICIP.2007.4379793
Filename
4379793
Link To Document