Title :
Structured design-for-debug-the SuperSPARC II methodology and implementation
Author :
Hao, Hong ; Avra, Rick
Author_Institution :
Sun Microsyst. Inc., Mountain View, CA, USA
Abstract :
This paper describes a structured design-for-debug methodology that provides observability throughout an entire chip. It makes use of existing design-for-testability (DFT) features on the chip and is part of the overall DFT strategy. The implementation of the methodology on the SuperSPARC II microprocessor is described. This methodology has been instrumental in the successful silicon debug and timely shipment of the chip
Keywords :
VLSI; automatic testing; boundary scan testing; built-in self test; computer debugging; computer testing; design for manufacture; design for testability; integrated circuit testing; product development; reduced instruction set computing; BIST; SRAM test mode; SuperSPARC II microprocessor; VLSI; clock control; design-for-testability; full-scan; observability; on-chip cache arrays; silicon debug; structured design-for-debug methodology; superscalar microprocessor; timely shipment; Design for testability; Design methodology; Instruments; Integrated circuit testing; Microprocessors; Observability; Silicon; Sun; Very large scale integration; Wires;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529831
