An integration of memory-based analog signal generation into current DFT architectures

Author

Hawrysh, E.M. ; Roberts, Gordon W.

Author_Institution

Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

fYear

1996

fDate

20-25 Oct 1996

Firstpage

528

Lastpage

537

Abstract

One method for the testing of mixed analog/digital integrated circuits involves the digital encoding of analog signals into an aperiodic pulse-density-modulated (PDM) serial bit stream and using it to stimulate a device under test. This paper describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: RAM- and scan-based storage. Using such design-for-test logic as the 1149.1-1990 JTAG architecture and a typical RAMBIST controller these analog signal generation techniques can be added to digital ICs with minimal additional hardware overhead

Keywords

analogue integrated circuits; automatic testing; built-in self test; design for testability; fault diagnosis; integrated memory circuits; mixed analogue-digital integrated circuits; random-access storage; signal sampling; 1149.1-1990 JTAG architecture; DFT architectures; RAM-based storage; RAMBIST controller; analog test; aperiodic pulse-density-modulated serial bit stream; design-for-test logic; digital encoding; hardware overhead; memory-based analog signal generation; mixed analog/digital integrated circuits; periodic approximation; scan-based storage; stimulation; Circuit testing; Design for testability; Digital integrated circuits; Encoding; Hardware; Integrated circuit testing; Logic design; Logic devices; Pulse circuits; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1996. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-3541-4

Type

conf

DOI

10.1109/TEST.1996.557078

Filename

557078