A global algorithm for the partial scan design problem using circuit state information

A global partial scan design algorithm based on circuit state information is proposed. Valid states obtained via logic simulation are used to evaluate testability of the circuit. A testability measure based on the density of encoding is used to select scan flip flops, and the problem is formulated into an optimization problem. An algorithm is presented to obtain an initial partial scan design solution, and a variety of techniques are used to subsequently derive an optimal solution. The most significant technique used in the global algorithm is that a dynamic testability measure is adopted, which can greatly reduce the size of the search space and enhance the effectiveness of the search problem. The partial scan design method can greatly reduce potential backtracks during test generation. Experimental results demonstrate 100% test efficiency can be obtained for most circuits selecting fewer scan flip flops than other methods