Concatenated Reed-Solomon Code with Hamming Code for DRAM Controller

In this paper, we propose a concatenated Reed-Solomon code with a Hamming code for dynamic random access memory (DRAM) controller. The concatenated code consists of a Reed-Solomon outer code, two shortened Reed-Solomon codes, and a Hamming inner code. The proposed code takes the advantages of Reed-Solomon codes and Hamming codes to protect DRAM memory data against single event upsets and multiple bit upsets. At the byte error rate of 10^-7, the proposed decoder shows about 1.3 dB of coding gain over that of the conventional Reed-Solomon decoder. We implement the proposed concatenated Reed-Solomon code on a very large-scale integration (VLSI) chip with 0.13 ¿ m complementary metal oxide semiconductor (CMOS) standard cell library at a supply voltage of 1.2 V. The core area of proposed architecture is 1.12 mm² with the gate counts of 121,900. The synthesized result shows the maximum throughput of 1.71 Gbps and the measured power consumption of 69 mW at 259 MHz.