A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC Paper 24.3)

Author

Urard, P. ; Paumier, L. ; Georgelin, P. ; Michel, T. ; Lebars, V. ; Yeo, E. ; Gupta, B.

Author_Institution

STMicroelectron., Crolles, France

fYear

2005

fDate

13-17 June 2005

Firstpage

547

Lastpage

548

Abstract

A DVB-S2 compliant codec is implemented in both 130nm-8M and 90nm-7M low-leakage CMOS technologies. The system includes encoders and decoders for both low-density parity check (LDPC) codes and serially concatenated BCH codes. All requirements of the DVB-S2 standard are supported including code rates between 1/4 and 9/10, block sizes of either 16,200 bits or 64,800 bits, and four digital modulation options. The 130nm core design occupies 49.6mm2 and operates at 200MHz, while the 90nm core design occupies 15.8mm2 and operates at 300MHz.

Keywords

BCH codes; CMOS integrated circuits; digital video broadcasting; parity check codes; video codecs; 130 nm; 135 Mbit/s; 200 MHz; 300 MHz; 64800 bit; 90 nm; DVB-S2 compliant codec; LDPC code; decoders; digital modulation; encoders; low-density parity check; low-leakage CMOS; serially concatenated BCH codes; CMOS technology; Codecs; Computer languages; Decoding; Digital video broadcasting; Forward error correction; Parity check codes; Random access memory; Silicon; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings. 42nd

Print_ISBN

1-59593-058-2

Type

conf

DOI

10.1109/DAC.2005.193869

Filename

1510389

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2048864