Paradigm shift in ESD qualification

For more than 20 years, IC component level ESD requirements have essentially stayed constant, while the silicon technologies rapidly advanced and effective production control methods have vastly improved. The silicon area impact coming from the technology scaling, combined with the high speed circuit performance impact and the influence from the IC package technology advances, are making the ESD design to the current levels a constraint leading to permanent delays in the product innovative cycles. Todaypsilas enhanced control methods do not justify this ESD over-design. This paper will propose a paradigm shift to more realistic but safe ESD target levels based on field data collected from IC suppliers and contract manufacturers.