DocumentCode :
2049090
Title :
Faster and better global placement by a new transportation algorithm
Author :
Brenner, Ulrich ; Struzyna, Markus
Author_Institution :
Res. Inst. for Discrete Math., Bonn Univ., Germany
fYear :
2005
fDate :
13-17 June 2005
Firstpage :
591
Lastpage :
596
Abstract :
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the total quadratic netlength, we partition the chip area into regions and assign the circuits to them (meeting capacity constraints) such that the placement is changed as little as possible. The core routine of our placer is a new algorithm for the transportation problem that allows to compute efficiently the circuit assignments to the regions. We test our algorithm on a set of industrial designs with up to 3.6 millions of movable objects and two sets of artificial benchmarks showing that it produces excellent results. In terms of wirelength, we can improve the results of leading-edge placement tools by about 5%.
Keywords :
VLSI; integrated circuit layout; network routing; BonnPlace; VLSI placement algorithm; analytical-based placers; circuit assignments; global placement; partitioning-based placers; quadratic netlength; transportation algorithm; Algorithm design and analysis; Circuits; Costs; Mathematics; Partitioning algorithms; Permission; Quadratic programming; Routing; Transportation; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
Type :
conf
DOI :
10.1109/DAC.2005.193879
Filename :
1510399
Link To Document :
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