DocumentCode :
2049223
Title :
Construction of Regular and Irregular LDPC Codes using (n, {k1, k2}, 1) Block Design
Author :
Patil, Siddarama R. ; Pathak, Sant S.
Author_Institution :
Dept. of Electr. & Electron. Commun. Eng., IIT Kharagpur, Kharagpur, India
fYear :
2007
fDate :
24-27 Nov. 2007
Firstpage :
1555
Lastpage :
1558
Abstract :
In this paper, we construct regular and irregular LDPC codes using (n, {k 1, k 2}, 1)block design. The problem of designing regular and irregular structured LDPC codes that have good overall error performance for wide range of code rates and block sizes with attractive storage requirements is attempted. The codes constructed by this method have the girth at least 6 and they perform well with the sum-product iterative decoding algorithm. Further we analyze the constructed codes based on number of short cycles of the corresponding Tanner graph. The analysis shows that codes having small number of short cycles and a cycle structure which is not overly regular in their Tanner graph perform better. The presented codes are well structured and unlike random codes can lend themselves to a very low-complexity encoder and decoder implementation.
Keywords :
iterative decoding; parity check codes; Tanner graph; irregular LDPC codes block design; regular LDPC codes block design; sum-product iterative decoding algorithm; Algorithm design and analysis; Design engineering; Graphical models; Iterative algorithms; Iterative decoding; Parity check codes; Performance analysis; Signal design; Signal processing; Signal processing algorithms; Block Design; LDPC; Tanner graph; girth; sum-product algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing and Communications, 2007. ICSPC 2007. IEEE International Conference on
Conference_Location :
Dubai
Print_ISBN :
978-1-4244-1235-8
Electronic_ISBN :
978-1-4244-1236-5
Type :
conf
DOI :
10.1109/ICSPC.2007.4728629
Filename :
4728629
Link To Document :
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