Reliability issues in MuGFET nanodevices

In this paper we review some recent results on reliability of MuGFET nanodevices with different gate stacks, including polycrystalline-Si/SiON as well as deposited metal gate/high-k stacks. In the first part we show how we can get information on the interface quality of the sidewall and top interface of the devices, by using an adapted charge pumping technique on gated diode structures. Then we compare the TDDB behavior of MuGFET and planar devices and we will show that if adequate processing is used, the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown for different gate voltages and temperatures. Next we discuss the Bias Temperature Instability (BTI) behavior of MuGFET CMOS devices. Novel interface passivation techniques as well as the impact of different dielectric nitridation techniques on BTI are discussed, showing similar BTI dependence on Nitrogen incorporated in MuGFET dielectrics as in planar devices. Finally we also discuss the ESD performance of MuGFET devices and we demonstrate that reasonable intrinsic ESD performance can be obtained, but achieving this desired ESD-robustness is found to be critically dependent on various design and process parameters. As a result the design of ESD protection for FinFET technology appears to be a challenging task for the future.