Title :
A design for FPGA implementation of the probabilistic neural network
Author :
Minchin, Graham ; Zaknich, A.
Author_Institution :
Dept. of Electr. & Electron. Eng., Western Australia Univ., Nedlands, WA, Australia
Abstract :
A design concept is introduced for the implementation of the probabilistic neural network classifier using standard binary field programmable gate array logic. It is an efficient hardware design concept which substitutes fixed point binary valued vector components for real valued ones and uses a top hat spherical basis function in conjunction with a city block distance measure without significantly affecting classifier performance for some practical problems
Keywords :
feedforward neural nets; field programmable gate arrays; logic CAD; neural chips; probabilistic logic; FPGA implementation design; binary FPGA logic; city block distance measure; classifier performance; fixed point binary valued vector components; hardware design; probabilistic neural network classifier; real valued components; top hat spherical basis function; Equations; Field programmable gate arrays; Hardware; Logic circuits; Logic design; Logic devices; Logic testing; Neural networks; Parallel processing; Programmable logic arrays;
Conference_Titel :
Neural Information Processing, 1999. Proceedings. ICONIP '99. 6th International Conference on
Conference_Location :
Perth, WA
Print_ISBN :
0-7803-5871-6
DOI :
10.1109/ICONIP.1999.845654
