DocumentCode :
2049373
Title :
System-level energy-efficient dynamic task scheduling
Author :
Zhuo, Jianli ; Chakrabarti, Chaitali
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
fYear :
2005
fDate :
13-17 June 2005
Firstpage :
628
Lastpage :
631
Abstract :
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device energy consumption and thereby the system-level energy consumption. In this paper, we present dynamic task scheduling algorithms for periodic tasks that minimize the system-level energy (CPU energy + device standby energy). The algorithms use a combination of (i) optimal speed setting, which is the speed that minimizes the system energy for a specific task, and (ii) limited preemption which reduces the numbers of possible preemptions. For the case when the CPU power and device power are comparable, these algorithms achieve up to 43% energy savings, but only up to 12% over the non-DVS scheduling. If the device power is large compared to the CPU power, we show that DVS should not be employed.
Keywords :
low-power electronics; processor scheduling; CPU energy; DVS processor; device standby energy; dynamic task scheduling algorithms; dynamic voltage scaling; energy minimization; limited preemption; optimal scaling point; optimal speed setting; power design technique; processor energy reduction; system-level energy consumption; Dynamic scheduling; Dynamic voltage scaling; Energy consumption; Energy efficiency; Energy management; Operating systems; Permission; Processor scheduling; Scheduling algorithm; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
Type :
conf
DOI :
10.1109/DAC.2005.193887
Filename :
1510407
Link To Document :
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