Digital VLSI implementation of a multi-precision neural network classifier

Author

Bermak, Amine ; Martinez, Dominique

Author_Institution

Sch. of Eng. & Math., Edith Cowan Univ., Joondalup, WA, Australia

Volume

2

fYear

1999

fDate

1999

Firstpage

560

Abstract

A systolic multi-precision digital VLSI classifier referred to as “SysNeuro” is presented. Unlike the usual VLSI implementation of classifiers, this hardware has been designed to achieve variable precision computations. A hardware reconfiguration is obtained by using switch elements to change the hardware connection between adjacent 4 bit neuron building blocks. With this reconfiguration concept it is possible to either increase the precision by pooling together adjacent cells or to increase the number of neurons for low levels of precision. Moreover, the design is easily programmable and can be configured to any artificial neural network (ANN) topology in order to cover various kinds of application. The chip integrates 16/8/4 neurons with a corresponding precision of 4/8/16 bits. A prototype has been successfully realized using 0.7 μm CMOS technology

Keywords

CMOS digital integrated circuits; VLSI; neural chips; real-time systems; systolic arrays; 0.7 mum; 4 to 16 bit; SysNeuro; artificial neural network topology; digital VLSI implementation; hardware connection; hardware reconfiguration; multi-precision neural network classifier; neuron building blocks; neurons; programmable design; switch elements; systolic multi-precision digital VLSI classifier; variable precision computations; Artificial neural networks; CMOS technology; Gas detectors; Hardware; Network topology; Neural networks; Neurons; Sensor fusion; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Information Processing, 1999. Proceedings. ICONIP '99. 6th International Conference on

Conference_Location

Perth, WA

Print_ISBN

0-7803-5871-6

Type

conf

DOI

10.1109/ICONIP.1999.845655

Filename

845655