Title :
Effective capacitance macro-modelling for architectural-level power estimation
Author :
Khellah, Muhammad M. ; Elmasry, M.I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
This paper presents a simple, yet efficient method to characterize the effective capacitance in data-path macros for architectural-level power estimation. Given a library of hard-macros, a capacitance model based on linear regression is derived for each macro. A transistor-level tool is employed for capacitance extraction. The capacitance models can be used during architectural-level power estimation. Unlike previous approaches, our characterization methodology assumes no specific word-level statistics of the input data, requires little knowledge about the structure of the modules, allows the user to trade-off accuracy and characterization time, and propagates effective capacitance directly from transistor-level (real) implementations. Simulation experiments on a set of data-path components with various sizes are performed. Compared to a previously published approach, our scheme significantly improves the accuracy of RTL power estimation and produces results within 15% from a transistor-level tool on the average
Keywords :
MOS digital integrated circuits; VLSI; capacitance; circuit CAD; high level synthesis; integrated circuit design; statistical analysis; RTL power estimation; architectural-level power estimation; capacitance extraction; capacitance macro-modelling; data-path components; data-path macros; effective capacitance; linear regression; transistor-level tool; Capacitance; Circuit simulation; Data mining; Digital circuits; Energy consumption; Libraries; Linear regression; Power dissipation; Power system reliability; Statistics;
Conference_Titel :
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-8409-7
DOI :
10.1109/GLSV.1998.665336