Performance evaluation of parallel architectures in real-time implementation of adaptive filtering algorithms

Explores the real-time performance of a number of parallel and sequential hardware architectures for the LMS and RLS adaptive filters. Throughout the investigations, it is seen that the C40+C40 based architecture with its powerful DSP resources performs as the fastest computing domain for both algorithms. The disparity among the relative processing times indicates a mismatch between the hardware requirements of the algorithms and the hardware resources of the architectures. Therefore, to fully exploit the architectures a close match needs to be forged between the algorithm and the underlying hardware, and issues such as algorithmic regularity and granularity need to be considered during an implementation process. A comparative performance of architectures demonstrated the need for utilisation of fast DSP and PP techniques in signal processing applications which involve complex and computationally intensive algorithms.<>