A novel technique for mitigating neutron-induced multi -cell upset by means of back bias

Author

Nakauchi, Takuya ; Mikami, Nobukazu ; Oyama, Akira ; Kobayashi, Hajime ; Usui, Hiroki ; Kase, Jun

Author_Institution

Sony Corp., Atsugi

fYear

2008

fDate

April 27 2008-May 1 2008

Firstpage

187

Lastpage

191

Abstract

We investigated the effect of back bias (V_BB) on neutron-induced multi-cell upset (MCU) in 65 nm low stand-by power SRAM. MCUs containing characteristic even number upsets were observed, and they were strongly related to the memory cell array layout. We concluded that most MCUs were induced by activation of parasitic lateral npn-bipolar transistors. We also found that MCU could be drastically reduced by supplying V_BB in the p-wells. The SER of MCU was reduced to 1/10 by supplying V_BB = -2.0 V in the p-wells without any modification of error checking and correction (ECC) circuits.

Keywords

SRAM chips; bipolar transistors; back bias effect; error checking and correction circuits; memory cell array layout; neutron-induced multicell upset; parasitic lateral npn-bipolar transistors; stand-by power SRAM; CMOS technology; Equivalent circuits; Error correction; Error correction codes; Neutrons; Nuclear power generation; Performance evaluation; Random access memory; Testing; Variable structure systems; ECC; MCU; SER; SRAM; back bias; multi-cell upset; neutron; parasitic bipolar transistor; soft error;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2008. IRPS 2008. IEEE International

Conference_Location

Phoenix, AZ

Print_ISBN

978-1-4244-2049-0

Electronic_ISBN

978-1-4244-2050-6

Type

conf

DOI

10.1109/RELPHY.2008.4558883

Filename

4558883