Title :
DFT & ATPG: together again
Author :
Mathew, Bini ; Saab, Daniel G.
Author_Institution :
MIPS Technol. Inc., Mountain View, CA, USA
Abstract :
A system which adds DFT and generates test vectors for the enhanced circuit is described. Partial reset, observability enhancement and partial scan are employed. A dynamic partial reset flip-flop selection method is described utilizing a fast genetic algorithm based sequential test generator. This system trades off various parameters to obtain high fault coverage, low test application times, low hardware overhead and low CPU time
Keywords :
VLSI; automatic test software; boundary scan testing; built-in self test; design for testability; fault diagnosis; flip-flops; genetic algorithms; logic CAD; logic testing; sequential circuits; ATPG; BIST; DFT; VLSI; dynamic partial reset flip-flop selection method; enhanced circuit; fast genetic algorithm; high fault coverage; low CPU time; low hardware overhead; low test application times; observability enhancement; partial scan; sequential test generator; simulation-based algorithms; test vector generation; Automatic test pattern generation; Circuit faults; Circuit testing; Controllability; Design for testability; Flip-flops; Hardware; Observability; Sequential analysis; System testing;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529841
