DocumentCode
2049787
Title
A variation-tolerant sub-threshold design approach
Author
Jayakumar, Nikhil ; Khatri, Sunil P.
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fYear
2005
fDate
13-17 June 2005
Firstpage
716
Lastpage
719
Abstract
Due to their extreme low power consumption, subthreshold design approaches are appealing for a widening class of applications which demand low power consumption and can tolerate larger circuit delays. However, subthreshold circuits are extremely sensitive to variations in supply, temperature and processing factors. In this paper, we present a subthreshold design methodology which dynamically self-adjusts for inter and intra-die process, supply voltage and temperature (PVT) variations. This adjustment is achieved by performing bulk voltage adjustments in a closed-loop fashion, using a charge pump and a phase-detector.
Keywords
VLSI; integrated circuit design; logic design; programmable logic arrays; PVT variations; bulk voltage adjustments; charge pump; circuit delays; extreme low power consumption; interdie process; intradie process; phase-detector; processing factors variations; self-adjusting subthreshold design; subthreshold circuits; supply voltage variations; temperature variations; variation-tolerant sub-threshold design; Charge pumps; Circuits; Delay; Design methodology; Energy consumption; Permission; Sun; Temperature sensors; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN
1-59593-058-2
Type
conf
DOI
10.1109/DAC.2005.193905
Filename
1510425
Link To Document