DocumentCode :
2050200
Title :
StressTest: an automatic approach to test generation via activity monitors
Author :
Wagner, Ilya ; Bertacco, Valeria ; Austin, Todd
Author_Institution :
Adv. Comput. Archit. Lab, Michigan Univ., Ann Arbor, MI, USA
fYear :
2005
fDate :
13-17 June 2005
Firstpage :
783
Lastpage :
788
Abstract :
The challenge of verifying a modern microprocessor design is an overwhelming one: increasingly complex micro-architectures combined with heavy time-to-market pressure have forced microprocessor vendors to employ immense verification teams in the hope of finding the most critical bugs in a timely manner. Unfortunately, too often size doesn´t seem to matter for verification teams, as design schedules continue to slip and microprocessors find their way to the marketplace with design errors. In this paper, we describe a simulation-based random test generation tool, called StressTest, that provides assistance in locating hard-to-find corner-case design bugs and performance problems. StressTest is based on a Markov-model-driven random instruction generator with activity monitors. The model is generated from the user-specified template programs and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity points within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov model into one that effectively stresses the points of interest. In parallel, StressTest monitors the correctness of the DUT response to the supplied stimuli, and if the design behaves unexpectedly, a bug and a trace that leads to it are reported. Using two micro-architectures as example testbeds, we demonstrate that StressTest finds more bugs with less effort than open-loop random instruction test generation techniques.
Keywords :
Markov processes; automatic test pattern generation; circuit simulation; formal verification; integrated circuit testing; logic testing; microprocessor chips; parallel architectures; performance evaluation; Markov processes; Markov-model-driven random instruction generator; StressTest; activity monitors; automatic test generation; automatic test pattern generation; circuit simulation; closed-loop feedback techniques; corner-case design bugs; design under test; formal verification; integrated circuit testing; logic testing; micro-architectures; microprocessor chips; microprocessor design; parallel architectures; performance evaluation; simulation-based random test generation tool; Analytical models; Automatic testing; Computer architecture; Computer bugs; Computer displays; Formal verification; Logic testing; Microprocessors; Permission; Processor scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
Type :
conf
DOI :
10.1109/DAC.2005.193922
Filename :
1510442
Link To Document :
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