Title :
ASIC yield estimation at early design cycle
Author :
Kim, Vonkyoung ; Tegethoff, Mick ; Chen, Tom
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit yield; parameter estimation; ASIC yield estimation; CMOS bridge fault model; design cycle; sensitive area model; Application specific integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Costs; Integrated circuit modeling; Logic testing; Predictive models; Virtual manufacturing; Yield estimation;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557110
