Is high level test synthesis just design for test?

High level synthesis (HLS) is defined as a topdown translation from the behavioral domain to the structural domain where the circuit is represented by a set of connected storage elements and functional units for the datapath and a logic level specification of the corresponding control unit. Testing is a bottom up approach process aiming at detecting realistic faults. Realistic faults depend on the physical domain, the technology process data and on the geometry of inner structures (inductive fault analysis). HLS cannot solve all the testing problems, but it may facilitate solutions by providing easier control or observation of internal units. Furthermore, the so produced designs exhibit less area and speed penalties than those obtained by applying a posteriori DFT techniques on synthetized gate level descriptions