DocumentCode
2051387
Title
A pipeline TDC module with TMC-PHX1 LSI
Author
Arai, Yutaro ; Ikeno, M. ; Fukuda, M. ; Emura, T.
Author_Institution
Nat. High Energy Accel. Res. Organ., Ibaraki, Japan
Volume
2
fYear
1999
fDate
1999
Firstpage
749
Abstract
A new 32-channel pipeline TDC module, which implements custom-developed Time Memory Cell LSIs, has been developed for high-rate wire-chamber applications. Time resolution of the module is 300 ps r.m.s., and the time range is 6.4 μsec. For handling data transfer and controlling the module, a 40 MHz digital signal processor is implemented in the module. Most of the control logic is implemented in two complex PLDs to achieve a density of 32 channels in a single-width, double height VME module
Keywords
analogue-digital conversion; drift chambers; nuclear electronics; programmable logic devices; readout electronics; 40 MHz; TMC-PHX1 LSI; custom-developed time memory cell LSIs; digital signal processor; high-rate wire-chamber applications; pipeline TDC module; single-width double height VME module; time resolution; CMOS technology; Computer buffers; Digital signal processing chips; Large scale integration; Logic; Phase locked loops; Pipelines; Signal resolution; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium, 1999. Conference Record. 1999 IEEE
Conference_Location
Seattle, WA
ISSN
1082-3654
Print_ISBN
0-7803-5696-9
Type
conf
DOI
10.1109/NSSMIC.1999.845776
Filename
845776
Link To Document