• DocumentCode
    2051679
  • Title

    Single step undirected reconfigurable networks

  • Author

    Ben-Asher, Yosi ; Schuster, Assaf

  • Author_Institution
    Dept. of Math. & Comput. Sci., Haifa Univ., Israel
  • fYear
    1997
  • fDate
    18-21 Dec 1997
  • Firstpage
    284
  • Lastpage
    289
  • Abstract
    The reconfigurable mesh (RN-MESH) can solve a large class of problems in constant time, including problems that require logarithmic time by other, even shared memory, models such as the PRAM with a similar number of processors. In this work we show that for the RN-MESH these constants can always be reduced to one, still using a polynomial number of processors. Given a reconfigurable mesh that computes a set of values in constant time, we show that it can be simulated by a single step reconfigurable mesh with maximum size that is polynomial in the size of the original mesh. The proof is constructive, where the construction of the single step RN-MESH holds for the relatively weak undirected RN-MESH model. In this model broadcasts made on buses arrive at all nodes that belong to the undirected connected component of the transmitting processor. A result similar to the one that is obtained in this work was previously obtained for the directed reconfigurable mesh model (DRN) (Ben-Asher and Schuster, 1996). However, the construction for the DRN-MESH relies on the fact that the buses are directed, and thus cannot be applied to the undirected case. In addition, the construction presented is simpler and uses significantly fewer processors than the one obtained for the DRN-MESH
  • Keywords
    computational complexity; graph theory; multiprocessor interconnection networks; parallel architectures; performance evaluation; reconfigurable architectures; system buses; PRAM; RN-MESH; broadcasts; constant time; directed reconfigurable mesh model; graph theory; logarithmic time; maximum size; multiprocessor interconnection network; reconfigurable mesh; shared memory models; single step undirected reconfigurable networks; system buses; undirected connected component; Acceleration; Broadcasting; Circuit simulation; Computational modeling; Computer networks; Computer science; Joining processes; Phase change random access memory; Polynomials; Sampling methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computing, 1997. Proceedings. Fourth International Conference on
  • Conference_Location
    Bangalore
  • Print_ISBN
    0-8186-8067-9
  • Type

    conf

  • DOI
    10.1109/HIPC.1997.634504
  • Filename
    634504