Characterization and modeling of ESD-behavior of multi layer ceramic capacitors

Filter networks consisting of a Multilayer Ceramic Capacitor (MLCC) and maybe a resistor are commonly used as off-chip ESD-protection. It is generally known that MLCCs lose their capacitance at higher voltages. Additionally, repeated exposure to ESD can cause irreversible parameter shifts or physical damage to MLCC. The consequences of these effects may cause insufficient ESD robustness or - more critical - result in a malfunction of the system to be protected. In this paper methods are proposed to characterize the behavior of MLCCs at higher voltages and to quantify the degradation due to pulse load. The measured parameters are used for an accurate high voltage capacitor model. The model was applied in different setups. Simulation results were compared to measurements in order to prove the proposed approach.