DocumentCode
2051938
Title
An energy-efficient and robust millimeter-wave Wireless Network-on-Chip architecture
Author
Mansoor, Nafees ; Ganguly, Anshuman ; Yuvaraj, Manoj Prashanth
Author_Institution
Rochester Inst. of Technol., Rochester, NY, USA
fYear
2013
fDate
2-4 Oct. 2013
Firstpage
19
Lastpage
24
Abstract
Millimeter-wave (mm-wave) wireless interconnects have emerged as a promising solution to the energy-latency issues of global interconnects. Wireless Network-on-Chip (WiNoC) architectures with CMOS compatible mm-wave transceivers can achieve significant improvements in performance and energy-efficiency in on-chip data transfer for multicore chips. A token-based medium access mechanism is used in several mm-wave WiNoC architectures to enable a distributed and optimal utilization of the available wireless bandwidth among multiple transmitters. However, on-chip wireless interconnects being an emerging technology can suffer from high rates of failures. High frequency transceivers are especially vulnerable to noise. Consequently, failure of the token passing mechanism can significantly degrade the potential benefits of this novel interconnect technology. Traditional error correction mechanisms are not sufficient to recover from such errors as these can completely disable access to the wireless medium or result in excessive data corruption. On the other hand naturally occurring small-world networks are known to be highly efficient as well as inherently resilient to high rates of failures of nodes and links. Hence, in this paper, we propose the design of a small-world mm-wave WiNoC architecture augmented with a robust token management scheme to overcome the consequences of such failures while incurring marginal overheads.
Keywords
CMOS integrated circuits; integrated circuit interconnections; millimetre wave integrated circuits; network-on-chip; radio transceivers; CMOS compatible mm-wave transceivers; energy efficiency; error correction; millimeter-wave wireless interconnects; millimeter-wave wireless network-on-chip architecture; token-based medium access mechanism; Discrete Fourier transforms; Fault tolerance; Fault tolerant systems; Nanotechnology; Very large scale integration; Network-on-Chip; robustness; token-passing; wireless interconnect;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location
New York City, NY
ISSN
1550-5774
Print_ISBN
978-1-4799-1583-5
Type
conf
DOI
10.1109/DFT.2013.6653577
Filename
6653577
Link To Document