Dielectric breakdown in a 45 nm high-k/metal gate process technology

Author

Prasad, C. ; Agostinelli, M. ; Auth, C. ; Brazier, M. ; Chau, R. ; Dewey, G. ; Ghani, T. ; Hattendorf, M. ; Hicks, J. ; Jopling, J. ; Kavalieros, J. ; Kotlyar, R. ; Kuhn, M. ; Kuhn, K. ; Maiz, J. ; Mcintyre, B. ; Metz, M. ; Mistry, K. ; Pae, S. ; Rachmady

Author_Institution

Intel Corp., Hillsboro, OR

fYear

2008

fDate

April 27 2008-May 1 2008

Firstpage

667

Lastpage

668

Abstract

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

Keywords

electric breakdown; high-k dielectric thin films; SILC degradation; SILC growth; SiON; TDDB lifetimes; dielectric breakdown; high-K/metal gate process; polarity dependent breakdown; size 45 nm; stress data collection; Dielectric breakdown; Dielectric substrates; Electric breakdown; Electrodes; Electron traps; Gate leakage; High K dielectric materials; High-K gate dielectrics; Logic; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2008. IRPS 2008. IEEE International

Conference_Location

Phoenix, AZ

Print_ISBN

978-1-4244-2049-0

Electronic_ISBN

978-1-4244-2050-6

Type

conf

DOI

10.1109/RELPHY.2008.4558979

Filename

4558979