DocumentCode
2052128
Title
Analysing degradation effects in charge-redistribution SAR ADCs
Author
Khan, Muhammad Asad ; Kerkhoff, Hans G.
Author_Institution
Testable Design & Test of Integrated Syst. (TDT) Group, Univ. of Twente, Enschede, Netherlands
fYear
2013
fDate
2-4 Oct. 2013
Firstpage
65
Lastpage
70
Abstract
Aging-sensitive technology nodes that are resulting in performance degradations in their electronic system implementations require aging simulations in advance for a more dependable design. Simulating time-domain aging effects in these electronic systems, especially in complex analog and mixed-signal systems like analog-to-digital converters, are time consuming and is often impossible for larger designs. The current paper investigates the degradation effects in the performance parameters of a mixed-signal system, a charge-redistribution successive approximation register (SAR) ADC, by using a system-level approach. In this approach the whole system has been divided into its sub-building blocks and the degradation effects of each individual building block have been incorporated into its system-level models. Furthermore, these system-level models have been simulated in LabVIEW in order to investigate the aging effects in static and dynamic performance parameters of a charge-redistribution SAR ADC due to the degradation in its building blocks. The sensitivity of the different static and dynamic performance parameters of the modelled ADC show that the presented technique is efficient to provide information about the aging effects to mixed-signal system designers and that they can use it to produce a more dependable design.
Keywords
ageing; analogue-digital conversion; network synthesis; virtual instrumentation; LabVIEW; aging effects; building blocks; charge-redistribution SAR ADC; charge-redistribution successive approximation register ADC; degradation effects; dynamic performance; mixed-signal system; static performance; system-level approach; Aging; Degradation; Discrete Fourier transforms; Fault tolerance; Fault tolerant systems; Performance evaluation; charge-redistribution SAR ADC; degradation analysis; degradation modelling; dependable design; sensitivity analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location
New York City, NY
ISSN
1550-5774
Print_ISBN
978-1-4799-1583-5
Type
conf
DOI
10.1109/DFT.2013.6653584
Filename
6653584
Link To Document