A cross-layer fault-tolerant design method for high manufacturing yield and system reliability

This paper describes a cross-layer design method for digital circuit fault-tolerant design. This cross-layer hierarchical scheme mainly contains selective duplication in logic level and spare cache design in micro-architecture level, working together seamlessly. When compared to traditional fault tolerance techniques, this method takes advantage of information from different circuit design levels to generate an effective solution. It also has great potential to work with other circuit design levels (e.g., core level) to meet the high demand in system reliability and robustness. Experimental results obtained using an ARM core instruction decoder demonstrate that, on average, the number of fault-free circuits is increased 250% by selectively duplicating 25% of the decoder. On top of selective duplication in logic level, adding a spare cache with 5 to 20 cache lines in micro-architecture level can further increase the number of fault-free circuits by 0.66 to 49.83 times depending on different number of defects injected.