Title :
Avoiding unknown states when scanning mutually exclusive latches
Author :
Pateras, Stephen ; Schmookler, Martin S.
Author_Institution :
Logic Vision, San Jose, CA, USA
Abstract :
Many modern circuits contain logic which must be controlled with mutually exclusive (one-out-of-n) control signals. Common examples include controls to 3-state buses and pass-gate multiplexers. If these control signals are allowed to attain any value combination other than one-out-of-n, the controlled logic may produce an unknown (X) state. In a scan based design, these mutually exclusive signals become problematic if they must be stored in latches. Mutually exclusive values will typically not be maintained on the outputs of these latches during scanning, nor as final values if random test patterns are scanned in. This paper describes a hardware technique that places logic in the scan path to ensure that a given set of latches always maintains mutually exclusive values during scanning
Keywords :
design for testability; logic testing; multiplexing; multiplexing equipment; system buses; 3-state buses; design for testability; mutually exclusive latches; one-out-of-n control signals; pass-gate multiplexers; scannable orthogonal latches; unknown states; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Control systems; Hardware; Latches; Logic circuits; Modems; Multiplexing;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529855