A low cost reliable architecture for S-Boxes in AES processors

This paper presents a fault-tolerant architecture for AES processors in order to mitigate the reliability issues introduced by the continued shrinking of CMOS technology. We concentrate on the faults occurring on S-Boxes which consume the largest hardware in AES processor. This hybrid solution combines time redundancy and hardware redundancy strategies for masking all single transient and permanent faults. By exploiting the inherent redundancy of AES processor with parallel implementation, the proposed solution limits the area overhead and overcomes many popular fault-tolerant techniques such as Triple Modular Redundancy approach and Triple Temporal Redundancy approaches.