A flexible co-processing approach for SoC-FPGAs based on dynamic partial reconfiguration and bitstream relocation methods

Today´s FPGAs merge the inherent demands on performance and flexibility more efficiently than ever before. Besides the integration of multi-core processors these SoC devices support dynamic partial reconfiguration of their fabric. Nevertheless, this technology is barely exploited in industrial projects. Major reasons for this position are a lack of design automation and missing abstraction layers. This paper addresses this issue and presents a co-processing framework taking advantage of dynamic reconfiguration while hiding the underlying complexity. At a low level, bitstream relocation methods are provided for Xilinx´s 7 series devices, inherently leveraging the system´s flexibility and resource utilization. The proposed framework finally provides a set of on-demand reconfigurable co-processing units to a SW-based processing system. This lightweight library based approach offers hardware acceleration for computationally intensive tasks by simple function calls as part of a software design.