• DocumentCode
    2052530
  • Title

    Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes

  • Author

    Reviriego, Pedro ; Liu, Siyuan ; Maestro, Juan Antonio ; Lee, Sang-Rim ; Touba, Nur A. ; Datta, Rohit

  • Author_Institution
    Univ. Antonio de Nebrija, Madrid, Spain
  • fYear
    2013
  • fDate
    2-4 Oct. 2013
  • Firstpage
    167
  • Lastpage
    171
  • Abstract
    Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.
  • Keywords
    circuit complexity; decoding; error correction codes; orthogonal codes; ECC; MCU; OLSC decoding algorithm; SEC codes; bit error; circuit complexity; data corruption; double error correction orthogonal Latin squares codes; memories; multiple cell upsets; random errors; single error correction; single memory cell; soft errors; triple adjacent error correction; Discrete Fourier transforms; Fault tolerance; Fault tolerant systems; Nanotechnology; Very large scale integration; Error correction codes; Multiple Cell Upsets (MCUs); majority logic decoding; memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
  • Conference_Location
    New York City, NY
  • ISSN
    1550-5774
  • Print_ISBN
    978-1-4799-1583-5
  • Type

    conf

  • DOI
    10.1109/DFT.2013.6653601
  • Filename
    6653601