DocumentCode
2052532
Title
Delay-power product simulation results for one-hot residue number system arithmetic circuits
Author
Chren, W.A., Jr. ; Brogdon, C.H. ; Andrevska, D.
Author_Institution
Lab. for VLSI Dev., Grand Valley State Univ., USA
Volume
1
fYear
1996
fDate
18-21 Aug 1996
Firstpage
544
Abstract
We present Spice simulations which verify previous analytical estimates of the delay-power product of One-Hot Residue adders and multipliers. These simulations show greater than a 50% reduction in the product below binary adders and an order of magnitude reduction for multipliers. Analytical models are derived from these results. They can be used to predict performance for larger moduli
Keywords
SPICE; adders; circuit analysis computing; delays; digital simulation; multiplying circuits; residue number systems; Spice simulations; adders; analytical models; arithmetic circuits; delay-power product simulation; multipliers; one-hot residue number system; Adders; Arithmetic; Circuit simulation; Degradation; Delay; Inverters; Rails; Switches; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location
Ames, IA
Print_ISBN
0-7803-3636-4
Type
conf
DOI
10.1109/MWSCAS.1996.594237
Filename
594237
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