Title :
Impact of mid-bond testing in 3D stacked ICs
Author :
Taouil, Mottaqiallah ; Hamdioui, Said ; Marinissen, Erik Jan ; Bhawmik, Sudipta
Author_Institution :
Fac. of EE, Math. & CS, Delft Univ. of Technol., Delft, Netherlands
Abstract :
In contrast to planar ICs, during the manufacturing of three-dimensional stacked ICs (3D-SICs) several tests such as pre-bond, mid-bond, post-bond and final tests can be applied. This in turn results into a huge number of test flows/strategies. Selecting appropriate and efficient test flow (for given design and manufacturing parameters such as stack size, die yield, stack yield, etc) is crucial for overall cost optimization. To evaluate the test flows, a case study is performed in which 3D-COSTAR is used to compare the overall cost of producing a 3D-SIC using variable fault coverage during the mid-bond tests. In addition, we investigate the impact of the logistics cost for various test flows. The impact of logistics costs depend on the outsourced processing steps during the manufacturing. Simulation results show, for our parameters, that by choosing an appropriate test flow the overall 3D-SIC cost for appropriate fault coverages can reduce the overall cost up to 20% for a 5-layered 3D-SIC with die yields of 90%.
Keywords :
fault diagnosis; integrated circuit design; integrated circuit testing; integrated circuit yield; silicon compounds; three-dimensional integrated circuits; 3D stacked IC; 3D-COSTAR; 3D-SIC cost; SiC; cost optimization; cost reduction; die yields; fault coverages; logistics cost; manufacturing; mid-bond testing; outsourced processing steps; test flow; variable fault coverage; Companies; Logistics; Manufacturing; Packaging; Stacking; Testing; Three-dimensional displays; 3D integration; cost modeling; test cost; test flows;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location :
New York City, NY
Print_ISBN :
978-1-4799-1583-5
DOI :
10.1109/DFT.2013.6653603
