Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test

Conventional approaches for test architecture optimization are based on designing test access mechanisms (TAMs) and core wrappers for a particular test data bandwidth available from the tester. However, constructing three dimensional integrated circuits (3D-ICs) using known-good dies (KGD) and known-good stacks (KGS) requires pre-bond testing of die and optionally partial stack testing in addition to the final post-bond test. In each of these different test periods: pre-bond, partial stack, and final test, the test data bandwidth available for a particular die may be different. A test architecture optimized for one particular test data bandwidth may be very inefficient when the bandwidth changes. Previously proposed test optimization techniques for handling this involve designing different TAM architectures for pre-bond and post-bond test in order to minimize the test time for each different test data bandwidth. This paper describes an approach for designing a single TAM architecture with a “bandwidth adapter” on each die that can be used efficiently for multiple test data bandwidths. Experimental results are presented which show that this approach allows efficient test in all phases from pre-bond, multiple partial stack configurations, and post-bond.