Title :
RSA decryption using the one-hot residue number system
Author :
Chren, W.A., Jr. ; Brogdon, C.H.
Author_Institution :
Lab. for VLSI Dev., Grand Valley State Univ., USA
Abstract :
The design of an RSA decryption circuit which uses the One-Hot Residue Number System is presented. Large modulus adders and multipliers are described which reduce the area of previous (barrel shifter-based) designs while preserving their low power and speed. An analytical estimate of the delay-power product of the decryption circuit is computed
Keywords :
adders; delays; multiplying circuits; public key cryptography; residue number systems; RSA decryption; Rivest-Shamir-Adelman public-key cryptosystem; adders; decryption circuit; delay-power product; low power circuits; multipliers; one-hot residue number system; speed; Adders; Arithmetic; Circuits; Communication system security; Data security; Delay estimation; Dynamic range; Laboratories; Partitioning algorithms; Public key cryptography;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594238
