Title :
Novel hot-carrier AC-DC design guidelines for advanced CMOS nodes
Author :
Guerin, C. ; Huard, V. ; Parthasarathy, C. ; Roux, J.-M. ; Bravaix, A. ; Vincent, E.
Author_Institution :
STMicroelectronics, Toulon
fDate :
April 27 2008-May 1 2008
Abstract :
The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.
Keywords :
CMOS integrated circuits; hot carriers; integrated circuit testing; transistors; DC hot carrier stress lifetime; HC risk assessment; High Temperature Operating Lifetest; Wafer Level Reliability; advanced CMOS nodes; advanced nodes; circuit device; circuit lifetime; hot-carrier AC-DC design guidelines; supply voltage; transistor HC modeling; Degradation; Frequency; Guidelines; Hot carriers; Inverters; MOS devices; MOSFETs; Semiconductor device modeling; Stress; Voltage;
Conference_Titel :
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-2049-0
Electronic_ISBN :
978-1-4244-2050-6
DOI :
10.1109/RELPHY.2008.4559016
