Defect-oriented IC test and diagnosis using VHDL fault simulation

High quality VLSI products require defect-oriented testing, as a complementary test technique. As the design activity is supported by hardware description languages, like VHDL, testing activity needs to follow this trend. In this paper, a methodology for defect-oriented test preparation is proposed, which leads to realistic VHDL fault modeling, injection and simulation. Heuristics for pseudo-realistic fault list generation (at the top-down design phase) are introduced. Two new tools are presented, fanthom and fastpen, and used on benchmark circuits, in top-down and bottom-up scenarios, for VHDL fault simulation and test effectiveness evaluation. Finally, the methodology and tools are shown to be useful for defects diagnosis