Low power and area efficient Static Random Access Memory design using schmitt trigger

Static Random Access Memory (Static RAM or SRAM) is a type of RAM that holds data in a static form, that is, as long as the memory device has power. Unlike dynamic RAM, it does not need to refresh. In modern Trends, the demand for memory has been increases tremendously. Due to reduction in SRAM operating voltage, cell stability degradation. In this paper, a nine-transistor (9T) Static Random Access Memory (SRAM) bitcell for the low voltage and area constraint applications is proposed. It is well known that in sub-threshold regime, reliability and process variations are the main design challenges, and standard six-transistor (6T) SRAM bitcell fails to operate in sub-Vth but it provides lower power consumption during read operation. ST2 Bitcells offer low voltage operation with 2× area overhead. The proposed design has better read stability and improved process variation tolerant as compared to standard 6T SRAM and ST2 at low voltage.