Low power and area efficient Duty Cycle Corrector with sigma-delta analog to digital converter

A Duty Cycle Corrector (DCC) using a sigma-delta Analog to Digital Converter (ADC) is one of the high speed and low power method. The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, sigma delta ADC and an output buffer. In order to achieve fast duty-correction with a small area, sigma-delta ADC controller used as a duty cycle correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.12-μm CMOS technology. Duty-cycle correctors (DCCs) are adjusting the clock duty cycle to 50% with the help of duty cycle adjuster. The duty-cycle detector checks whether the positive duty-rate is greater than 50%. The operating frequency range of these DCC is 312.5MHz to 1GHz. DCC with sigma delta ADC gives advantages over other DCC´s are better duty-cycle accuracy, wider duty-correction range and short duty-correction time. The measured duty-cycle error is below 1%, within 320ps external input duty-cycle error. The duty cycle of output signal is corrected and it is less than 14 cycles.