• DocumentCode
    2053867
  • Title

    In-system testing of cache memories

  • Author

    Sosnowski, Janusz

  • Author_Institution
    Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
  • fYear
    1995
  • fDate
    21-25 Oct 1995
  • Firstpage
    384
  • Lastpage
    393
  • Abstract
    Caches embedded in microprocessor systems are implemented with limited observability and controllability. Hence they create many problems in testing. This paper gives a methodology of developing user test programs for data and instruction caches with various organization
  • Keywords
    built-in self test; cache storage; computer testing; integrated circuit testing; microprocessor chips; cache memories; controllability; data caches; in-system testing; instruction caches; microprocessor systems; observability; user test programs; Built-in self-test; Cache memory; Circuit testing; Computer science; Logic arrays; Logic testing; Microprocessors; Observability; Read-write memory; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1995. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2992-9
  • Type

    conf

  • DOI
    10.1109/TEST.1995.529864
  • Filename
    529864
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2053867