Title :
Orthogonal scan: low overhead scan for data paths
Author :
Norwood, Robert B. ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead-area, delay and test application time by sharing functional and test logic. Orthogonal scan paths are orthogonal to traditional scan paths. Judicious ordering of the registers in the orthogonal scan path can allow the scan path to be implemented entirely with existing interconnect, resulting in no additional wiring to connect the scan path and no performance degradation due to additional loading on the bistable outputs. Taking the orthogonal scan path into account during high-level synthesis operations such as register allocation allows for a better final solution, but orthogonal scan paths can also be used with non-synthesized data path. Orthogonal scan paths have roughly half the overhead of traditional scan paths and greatly reduce the test application time. TOPS, Stanford CRC´s synthesis-for-test tool, has been modified to implement orthogonal scan paths for synthesized circuits
Keywords :
automatic testing; boundary scan testing; design for testability; fault diagnosis; high level synthesis; integrated circuit testing; logic testing; TOPS; bistable outputs; data paths; high-level synthesis operations; low overhead scan; nonsynthesized data path; orthogonal scan paths; register allocation; test application time; test overhead-area; Circuit synthesis; Circuit testing; Cyclic redundancy check; Degradation; Delay effects; High level synthesis; Integrated circuit interconnections; Logic design; Logic testing; Wiring;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557123