Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time

A technique to save the frequency of write operation on the non-volatile memory is proposed for reducing dynamic power dissipation of non-volatile logic LSI which shortens its break-even time for power gating. The proposed technique is realized by combining a selective write method with a coding technique. The selective write method compares input words and stored words, and rejects redundant write operation. Moreover, the use of the data coding technique shortens the Hamming distance between adjacent words in an input data sequence and reduces the frequency of bit reversal in the non-volatile memory, which results in the further reduction in the power dissipation due to write operation. Through the design and evaluation of a non-volatile 8-bit counter, it is observed that the proposed technique shortens the break-even time for power gating by up to 85.2% with a small hardware overhead.