A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction

A multi-level cell for STT-MRAM is proposed using biaxial magnetic tunnel junction (MTJ). The proposed cell consists of one transistor and one MTJ (1T1MTJ) with biaxial magnetic layer to store two bits per cell. Using the four stable states of the biaxial layer, the proposed cell allows 2 bits to be stored per cell without voltage headroom limitations. Current pulses with different amplitudes are applied during write operation to switch the magnetization vector to the corresponding region. This avoids multi-step write operations required for previously proposed multi-level cells using uniaxial MTJs. On average, the simulated write speed of the proposed cell is 33% faster than that of previous work, and the proposed cell consumes 8% less power. Also, current sensing vs. voltage sensing is compared for the biaxial MTJ, Current sensing provides uniform distribution of the sense margin.