A new method for partial scan design based on propagation and justification requirements of faults

Scan design can be viewed as scanning flip-flops, so that faults, otherwise aborted, are detected by meeting propagation and justification requirements. In this paper, we propose a new method which identifies justification and propagation requirements of aborted faults through combinational test generation and selects flip-flops to meet the requirements. Two procedures, optimal and heuristic, were considered in the process. We implemented the heuristic procedure in a program called BELLONA. BELLONA selects flip-flops progressively to lead to high fault efficiency. Our experimental results show that BELLONA achieves 100% fault efficiency for all circuits experimented with, on average, 19% of flip-flops selected