DocumentCode
2054689
Title
A parallel implementation of a fast multipole based 3-D capacitance extraction program on distributed memory multicomputers
Author
Yuan, Yanhong ; Banerjee, Prithviraj
Author_Institution
Dept. of Electr. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
fYear
2000
fDate
2000
Firstpage
323
Lastpage
330
Abstract
Very fast and accurate 3-D capacitance extraction is essential for interconnect optimization in ultra deep sub-micro designs (UDSM). Parallel processing provides an approach to reducing the simulation turn-around time. This paper examines the parallelization of the well known fast multipole based 3-D capacitance extraction program FASTCAP, which employs new preconditioning and adaptive techniques. To account for the complicated data dependencies in the unstructured problems, we propose a generalized cost function model, which can be used to accurately measure the workload associated with each cube in the hierarchy. We then present two adaptive partitioning schemes, combined with efficient communication mechanisms with bounded buffer size, to reduce the parallel processing overhead. The overall load balance is achieved through balancing the load at each level of the multipole computation. We report detailed performance results using a variety of standard benchmarks on 3-D capacitance extraction, on an IBM SP2
Keywords
circuit CAD; integrated circuit interconnections; parallel programming; 3-D capacitance extraction; adaptive partitioning; interconnect optimization; parallel implementation; parallelization; ultra deep sub-micro designs; Capacitance; Concurrent computing; Conductors; Contracts; Costs; Design optimization; Integrated circuit interconnections; Parallel processing; Signal design; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2000. IPDPS 2000. Proceedings. 14th International
Conference_Location
Cancun
Print_ISBN
0-7695-0574-0
Type
conf
DOI
10.1109/IPDPS.2000.846002
Filename
846002
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