A QoS Guaranteed Cache Design for Environment Friendly Computing

Simultaneous multithreading (SMT) and chip-multiprocessor (CMP) are currently two important trends in the design of processors. As the processor executes more than two programs simultaneously, these programs will compete keenly for the use of the cache. This makes it more difficult to predict the worst case computation time (WCET), and might even lead to an overall low efficiency in certain circumstances. Even though the traditional cache partitioning method can solve the foregoing two problems, it reduces the utility rate of the cache as well as the performance of the processor. The method presented in this paper allows the processors to share the cache without affecting each other. It makes the WCET analysis more easily on a multithreaded CPU architecture (e.g., SMT and CMP). Furthermore, the idea of the cache design is based on a power-efficient (i.e., environment friendly) design called ``drowsy cache´´ and the power-efficiency feature is inherited.