A gate-array-based 666 MHz VLSI test system

Author

Kikuchi, Shuji ; Hayashi, Yoshihiko ; Suga, Takashi ; Saitou, Jun ; Kaneko, Masahiko ; Matsumoto, Takashi ; Yoshino, Ryozou

Author_Institution

Lab. of Production Eng. Res., Hitachi Ltd., Kanagawa, Japan

fYear

1995

fDate

21-25 Oct 1995

Firstpage

451

Lastpage

458

Abstract

A 666 MHz VLSI test system with a dedicated memory test pattern generator was developed. A loose-timing data transfer scheme was employed for better integration of a shared-resource unit into the per-pin tester-architecture, Timing control resolution of 12.5 ps was achieved within a normal framework of a gate array LSI. A simple and low-cost timing calibration-technique was developed to offer accurate test timings. Parallel operation of the memory test pattern generators was used to realize a non-interrupted pattern generation at the maximum speed

Keywords

VLSI; automatic test equipment; calibration; computer architecture; computer testing; integrated circuit testing; integrated memory circuits; logic arrays; reduced instruction set computing; timing; 666 MHz; RISC; VLSI test; dedicated memory test pattern generator; gate array LSI; gate-array VLSI test; integration; loose-timing data transfer; low-cost timing calibration; parallel operation; per-pin tester-architectur; shared-resource; speed; test timings; timing control resolution; Calibration; Circuit testing; Clocks; Large scale integration; Logic testing; Reduced instruction set computing; System testing; Test pattern generators; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529872

Filename

529872