A low-cost high-performance CMOS timing vernier for ATE

Current conditions within the test industry impose a difficult combination of design requirements for the next generation of General Purpose Automatic Test Equipment: faster devices require higher tester bandwidth, higher data rates, and higher timing edge accuracy; yet, lower device selling prices and industry economics require lower ATE acquistion and maintenance costs. Emitter Coupled Logic (ECL) based timing systems can achieve high performance, but are expensive and power hungry. The use of CMOS-based ATE has become necessary in order to meet the lower-power and higher integration demands associated with lower cost. However methods of dealing with the high variability of a CMOS process and with the high temperature and voltage dependence of CMOS are required. A new timing vernier combining two different stabilization techniques has been developed using a 0.5 micron process which achieves high performance at low power and low cost