System level fault simulation

Author

Sanchez, P. ; Hidalgo, Isabel

Author_Institution

TEISA Dept., Cantabria Univ., Santander, Spain

fYear

1996

fDate

20-25 Oct 1996

Firstpage

732

Lastpage

740

Abstract

Gate level fault simulation has been a typical step in the ASIC design process but it cannot be used for real hardware/software systems in which there are multiple boards and chips, several test strategies, complex embedded systems in ASICs and different test procedures (hardware test pattern generation, software programs for hardware tests, etc.). This paper proposes a new methodology bared on VHDL which covers the new fault simulation demands of real digital systems

Keywords

application specific integrated circuits; circuit analysis computing; design for testability; digital simulation; fault diagnosis; hardware description languages; large-scale systems; logic testing; real-time systems; ASIC design; VHDL; complex embedded systems; fault simulation; gate level fault simulation; hardware test pattern generation; hardware tests; hardware/software systems; multiple boards; real digital systems; software programs; system level fault simulation; Application specific integrated circuits; Digital systems; Embedded software; Embedded system; Hardware; Process design; Software systems; Software testing; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1996. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-3541-4

Type

conf

DOI

10.1109/TEST.1996.557132

Filename

557132